A digital sense amplifier may be used as an edge-triggered latch, or flip-flop, that samples and holds a binary input signal. Ideally, the input signal is sampled by the sense amplifier instantaneously at a predetermined point on the rising edge of a clock signal. In practice, however, the sampling occurs over a finite time, and the input signal must be held constant while it is sampled. The time during which the input signal must be held constant before the rising edge of the clock signal is referred to as the "setup time," and the time it must be held constant after the rising edge is referred to as the "hold time."
If the input signal changes during the setup or hold times, the latch may produce output signals that are not at binary levels, that is, high or low signals that are not at supply voltage VDD (high) or VSS (low) levels, and are thus ambiguous. Alternatively, the latch may produce output signals that correspond to the input signal at some point in time other than the desired sample time, and thus, provide incorrect values to receiving circuitry.
The length of the setup and hold times limits the time during which circuitry that processes the input signals may operate. To provide signals to the latch, the processing circuitry can modify the input signals only during the portion of the clock cycle that follows the hold time associated with a previous sample time and precedes the setup time associated with a next sample period. At the next sample time the latched input signals may be sampled by a next latch, and then passed on to a next stage of processing circuitry, and so forth. The hold time imposes timing restrictions on the design that must be met for functionality. It is therefore desirable to minimize hold time on heavily used circuits, such as latches, to avoid signal timing issues that can cause the integrated circuit to fail to operate correctly.
Known prior circuits reduce, for example, hold time while at the same time increasing the setup time. These circuits thus require that the input signals be held stable for essentially the same relatively long period of time. It is therefore desirable to minimize hold time, without causing a corresponding increase in setup time.